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Description of Individual Course Units| Course Unit Code | Course Unit Title | Type of Course Unit | Year of Study | Semester | Number of ECTS Credits | | ELT1042010776 | DIGITAL DESIGN | Compulsory | 1 | 2 | 4 |
| | Level of Course Unit | | Short Cycle | | Objectives of the Course | | • to design various circuits by using Logic gates, flip-flops and integrated circuit components | | Name of Lecturer(s) | | Öğr. Gör. Begüm KORUNUR ENGİZ | | Learning Outcomes | | 1 | Knows operating and using multiplexer, demultiplexer, encoder, decoder, 7 segment display and driver, PLA, PAL IC's. | | 2 | Knows difference between sequential and combinational circuits. | | 3 | Knows operating and using of counter, rom, prom, eprom, eeprom and ram ic's |
| | Mode of Delivery | | Formal Education | | Prerequisites and co-requisities | | | Recommended Optional Programme Components | | Week 1 Logical operations and logic gates
Week 2 Logical functions and minterm, maxterm.
Week 3 Karnough diagrams.
Week 4 Resolving sample questions. Providing information about multiplexers and demultiplexers.
Week 5 Decoders.
Week 6 Introduction to sequential circuits. Comparing combinational and sequential logic circuits.
Week 7 SR, JK, T, D flip-flops.
Week 8 Resolving sample questions. – Midterm Exam.
Week 9 Introduction to PLA, PAL, ROM, PROM, EPROM IC's
Week 10 Designing circuits by using PLA, PAL, ROM, PROM and EPROM.
Week 11 Exam
Week 12 State diagrams. Analyzing a sequential circuit and obtaining its state diagram.
Week 13 Resolving sample questions.
Week 14 Counters and counter ic's.
Week 15 Final exam.
| | Course Contents | | • to learn Circuit Design by using Logic Gates
• to learn Circuit Design by using Flip-Flops
• to learn Circuit Design by Using Integrated
| | Weekly Detailed Course Contents | |
| 1 | Logical operations and logic gates | | | | 2 | Logical functions and minterm, maxterm. | | | | 3 | Karnough diagrams. | | | | 4 | Resolving sample questions. Providing information about multiplexers and demultiplexers. | | | | 5 | Decoders. | | | | 6 | Introduction to sequential circuits. Comparing combinational and sequential logic circuits. | | | | 7 | SR, JK, T, D flip-flops. | | | | 8 | Resolving sample questions. – Midterm Exam. | | | | 9 | Introduction to PLA, PAL, ROM, PROM, EPROM IC's | | | | 10 | Designing circuits by using PLA, PAL, ROM, PROM and EPROM. | | | | 11 | Designing circuits by using PLA, PAL, ROM, PROM and EPROM. | | | | 12 | State diagrams. Analyzing a sequential circuit and obtaining its state diagram. | | | | 13 | Resolving sample questions. | | | | 14 | Counters and counter ic's. | | | | 15 | Final exam. | | |
| | Recommended or Required Reading | | M. YAĞIMLI-F.AKAR, 2009. Dijital Elektronik
Moris Mano, 2002.Sayısal Tasarım | | Planned Learning Activities and Teaching Methods | | | Assessment Methods and Criteria | |
| SUM | 0 | |
| SUM | 0 | | Yarıyıl (Yıl) İçi Etkinlikleri | 40 | | Yarıyıl (Yıl) Sonu Etkinlikleri | 60 | | SUM | 100 |
| | Language of Instruction | | Turkish | | Work Placement(s) | |
| | Workload Calculation | |
| Midterm Examination | 1 | 1 | 1 | | Final Examination | 1 | 1 | 1 | | Attending Lectures | 14 | 4 | 56 | | Self Study | 14 | 3 | 42 | | Individual Study for Mid term Examination | 1 | 12 | 12 | | Individual Study for Final Examination | 1 | 8 | 8 | |
| Contribution of Learning Outcomes to Programme Outcomes | | LO1 | | | 5 | | | | | 5 | | | | | | | | | | LO2 | | | 5 | 5 | 5 | | | 5 | | | | | | | | | | LO3 | | | 5 | 5 | 5 | | | 5 | | | | | | | | |
| | * Contribution Level : 1 Very low 2 Low 3 Medium 4 High 5 Very High |
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